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The 8250/16450/16550 UART occupies eight contiguous I/O port addresses. In the IBM PC, there are two defined locations for these eight ports and they are known collectively as <filename>COM1</filename> and <filename>COM2</filename>. The makers of PC-clones and add-on cards have created two additional areas known as <filename>COM3</filename> and <filename>COM4</filename>, but these extra COM ports conflict with other hardware on some systems. The most common conflict is with video adapters that provide IBM 8514 emulation.
<filename>COM1</filename> is located from 0x3f8 to 0x3ff and normally uses IRQ 4. <filename>COM2</filename> is located from 0x2f8 to 0x2ff and normally uses IRQ 3. <filename>COM3</filename> is located from 0x3e8 to 0x3ef and has no standardized IRQ. <filename>COM4</filename> is located from 0x2e8 to 0x2ef and has no standardized IRQ.
A description of the I/O ports of the 8250/16450/16550 UART is provided below.
I/O Port
Access Allowed
+0x00
write (DLAB==0)
Transmit Holding Register (THR).
Information written to this port are treated as data words and will be transmitted by the UART.
read (DLAB==0)
Receive Buffer Register (RBR).
Any data words received by the UART form the serial link are accessed by the host by reading this port.
write/read (DLAB==1)
Divisor Latch LSB (DLL)
This value will be divided from the master input clock (in the IBM PC, the master clock is 1.8432MHz) and the resulting clock will determine the baud rate of the UART. This register holds bits 0 thru 7 of the divisor.
+0x01
Divisor Latch MSB (DLH)
This value will be divided from the master input clock (in the IBM PC, the master clock is 1.8432MHz) and the resulting clock will determine the baud rate of the UART. This register holds bits 8 thru 15 of the divisor.
write/read (DLAB==0)
Interrupt Enable Register (IER)
The 8250/16450/16550 UART classifies events into one of four categories. Each category can be configured to generate an interrupt when any of the events occurs. The 8250/16450/16550 UART generates a single external interrupt signal regardless of how many events in the enabled categories have occurred. It is up to the host processor to respond to the interrupt and then poll the enabled interrupt categories (usually all categories have interrupts enabled) to determine the true cause(s) of the interrupt.
Bit 7
Reserved, always 0.
Bit 6
Bit 5
Bit 4
Bit 3
Enable Modem Status Interrupt (EDSSI). Setting this bit to "1" allows the UART to generate an interrupt when a change occurs on one or more of the status lines.
Bit 2
Enable Receiver Line Status Interrupt (ELSI) Setting this bit to "1" causes the UART to generate an interrupt when the an error (or a BREAK signal) has been detected in the incoming data.
Bit 1

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Source string comment
(itstool) path: row/entry
Flags
read-only
Source string location
article.translate.xml:1212 article.translate.xml:1223
String age
a year ago
Source string age
a year ago
Translation file
articles/serial-uart.pot, string 283