Unit Instance

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    "source": [
        "FIFO Control Register (FCR) (This port does not exist on the 8250 and 16450 UART.) +\nBit 7 -> Receiver Trigger Bit #1 +\nBit 6 -> Receiver Trigger Bit #0 +\n\nThese two bits control at what point the receiver is to generate an interrupt when the FIFO is active. +\n7 6 How many words are received before an interrupt is generated +\n0 0 1 +\n0 1 4 +\n1 0 8 +\n1 1 14 +\nBit 5 -> Reserved, always 0. +\nBit 4 -> Reserved, always 0. +\nBit 3 -> DMA Mode Select. If Bit 0 is set to \"1\" (FIFOs enabled), setting this bit changes the operation of the -RXRDY and -TXRDY signals from Mode 0 to Mode 1. +\nBit 2 -> Transmit FIFO Reset. When a \"1\" is written to this bit, the contents of the FIFO are discarded. Any word currently being transmitted will be sent intact. This function is useful in aborting transfers. +\nBit 1 -> Receiver FIFO Reset. When a \"1\" is written to this bit, the contents of the FIFO are discarded. Any word currently being assembled in the shift register will be received intact. +\nBit 0 -> 16550 FIFO Enable. When set, both the transmit and receive FIFOs are enabled. Any contents in the holding register, shift registers or FIFOs are lost when FIFOs are enabled or disabled. +"
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    "location": "documentation/content/en/articles/serial-uart/_index.adoc:740",
    "context": "",
    "note": "type: Table",
    "flags": "no-wrap",
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    "state": 0,
    "fuzzy": false,
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    "position": 282,
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    "has_failing_check": false,
    "num_words": 237,
    "source_unit": "https://translate-dev.freebsd.org/api/units/1273006/?format=api",
    "priority": 100,
    "id": 1273720,
    "web_url": "https://translate-dev.freebsd.org/translate/documentation/articlesserial-uart_index/it_IT/?checksum=884295f17db8adf8",
    "url": "https://translate-dev.freebsd.org/api/units/1273720/?format=api",
    "explanation": "",
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    "pending": false,
    "timestamp": "2022-02-03T10:29:41.485946Z"
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