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Project website | wiki.freebsd.org/DocTranslationOnWeblate |
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Instructions for translators | https://wiki.freebsd.org/DocTranslationOnWeblate Mailing list for translators: <<freebsd-translators@freebsd.org> |
Translation process |
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Translation license | BSD-2-Clause-FreeBSD |
Filemask | articles/*/serial-uart.po |
Languages | 3 |
Source strings | 468 |
Source words | 9,234 |
Source characters | 57,144 |
Hosted strings | 1,404 |
Hosted words | 27,702 |
Hosted characters | 171,432 |
Error in Receiver FIFO. On the 8250/16450 UART, this bit is zero. This bit is set to "1" when any of the bytes in the FIFO have one or more of the following error conditions: PE, FE, or BI.
Error en el receptor FIFO. En el UART 8250/16450, este bit es cero. Este bit se establece en "1" cuando cualquiera de los bytes del FIFO tiene una o más de las siguientes condiciones de error: PE, FE o BI.
OUT 2. An auxiliary output that the host processor may set high or low. In the IBM PC serial adapter (and most clones), OUT 2 is used to tri-state (disable) the interrupt signal from the 8250/16450/16550 UART.
OUT 2. Una salida auxiliar que el procesador anfitrión puede establecer alta o baja. En el adaptador en serie de IBM PC (y en la mayoría de los clones), OUT 2 se usa para tri-estado (deshabilitar) la señal de interrupción del 8250/16450/16550 UART.
Loop-Back Enable. When set to "1", the UART transmitter and receiver are internally connected together to allow diagnostic operations. In addition, the UART modem control outputs are connected to the UART modem control inputs. CTS is connected to RTS, DTR is connected to DSR, OUT1 is connected to RI, and OUT 2 is connected to DCD.
Activar bucle invertido. Cuando se establece en "1", el transmisor y el receptor UART se conectan internamente para permitir operaciones de diagnóstico. Además, las salidas de control del módem UART están conectadas a las entradas de control del módem UART. CTS está conectado a RTS, DTR está conectado a DSR, OUT1 está conectado a RI y OUT 2 está conectado a DCD.